Single chip mixed memory for dynamic replacement of DRAM bad cell

摘要

A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.

主权项

1. A memory device comprising:
an interface device comprising:
an address input(s) configured to receive address information from an address stream of a host controller;an address output(s) configured to drive address information;an address match table comprising at least a revised address corresponding to a spare memory location;a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation, the control module configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location;a multiplexer coupled to the address input and coupled to the address output; a plurality of address inputs; a plurality of control inputs; a plurality of data input/outputs; a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells, each of the plurality of memory cells being coupled to a data input/output and free from any spare memory cells; and a spare group of memory cells comprising a plurality of spare memory cells separate from each of the plurality of memory arrays, each of the plurality of spare memory cells being dynamically addressable using the address match table by the plurality of memory arrays.