METHODS AND APPARATUS FOR DEBUGGING LOWEST POWER STATES IN SYSTEM-ON-CHIPS

摘要

Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

主权项

1. A method for debugging a finite state machine (FSM) that sequence System-On-Chips (SOCs) through lowest power states, comprising:
implementing an on-chip debug logic circuit; connecting the debug logic circuit to a power gate-able system on chip (SoC) voltage source; operating the finite state machine connected to the Always On voltage source to sequence the SoC through the lowest power state by moving from a low power state to a next low power state and generating respective output signals corresponding to the low power states; masking the output signals to generate respective masked output signals; applying the masked output signals to SoC circuit elements to prevent transitioning into low power states; applying the masked output signals to the debug circuit elements to prevent entering into reset state; and debugging the finite state machine in the lowest power state by the debug logic circuit.