Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

摘要

Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.

主权项

1. A system for correcting errors in data read from memory cells, comprising:
a memory controller, the memory controller has an encoder, and a decoder, the memory controller is configured to adjust a correctable raw bit error rate limit in response to different bit error rates occurring in data read from the memory cells; wherein the correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, and is subsequently adjusted by changing a number of soft bits allocated for message values during soft-decision decoding or changing a code-rate of a structured code.