Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data

摘要

A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N≠M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

主权项

1. A system, comprising:
first circuitry and second circuitry, configured to communicate with each other, the first circuitry being configured to:
generate a transmitter cyclic pattern having a pattern length of N bits and to convert the transmitter cyclic pattern into a M-bit transmitter parallel data stream, where each of N and M is an integer larger than one and N and M are different integers;alter a first sequence of bits in each word of the transmitter parallel data stream by performing a transmitter altering process including exchanging specified ones of the bits at specified positions within each word of the transmitter parallel data stream with each other and to generate a bit-sequence altered transmitter parallel data stream;convert the bit-sequence altered transmitter parallel data stream into a serial data in synchrony with a clock signal; andtransmit the serial data together with the clock signal to the second circuitry; the second circuitry being configured to:
convert the serial data received from the first circuitry into an M-bit receiver parallel data stream in synchrony with the clock signal;alter a second sequence of bits in each word of the receiver parallel data stream by performing a first receiver altering process opposite to the transmitter altering process, to generate a bit-sequence restored parallel data stream;generate a reference cyclic pattern by using bits in the bit sequence restored parallel data stream as initial values;convert the reference cyclic pattern into an M-bit reference parallel data stream;alter a third sequence of bits in each word of the reference parallel data stream by performing a second receiver altering process, which is the same as the transmitter altering process, to generate a bit-sequence altered reference parallel data stream; anddetect a bit shift error based on the first receiver altering process and the second receiver altering process, by comparing the receiver parallel data stream with the bit-sequence altered reference parallel data stream, the detection of the bit shift error occurring when the first sequence of bits does not match the third sequence of bits.