Extended defect sizing range for wafer inspection

摘要

Various embodiments for extended defect sizing range for wafer inspection are provided. One inspection system includes an illumination subsystem configured to direct light to the wafer. The system also includes an image sensor configured to detect light scattered from wafer defects and to generate output responsive to the scattered light. The image sensor is also configured to not have an anti-blooming feature such that when a pixel in the image sensor reaches full well capacity, excess charge flows from the pixel to one or more neighboring pixels in the image sensor. The system further includes a computer subsystem configured to detect the defects on the wafer using the output and to determine a size of the defects on the wafer using the output generated by a pixel and any neighboring pixels of the pixel to which the excess charge flows.

主权项

1. A system configured to inspect a wafer, comprising:
an illumination subsystem configured to direct light to the wafer; an image sensor configured to detect light scattered from wafer defects and to generate output responsive to the scattered light, wherein the image sensor is further configured to not have an anti-blooming feature such that when a pixel in the image sensor reaches full well capacity, excess charge flows from the pixel to one or more neighboring pixels in the image sensor; and a computer subsystem configured to detect the defects on the wafer using the output and to determine a size of the defects on the wafer using the output generated by a pixel and any neighboring pixels of the pixel to which the excess charge of the pixel flows, wherein the computer subsystem is further configured to determine the size of the defects by adding charges of the pixel and any neighboring pixels to which the excess charge of the pixel flows to determine a total charge and determining the size from the total charge.