发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer. |
申请公布号 |
US9082663(B2) |
申请公布日期 |
2015.07.14 |
申请号 |
US201213608042 |
申请日期 |
2012.09.10 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Isobe Atsuo;Sasaki Toshinari |
分类号 |
H01L29/78;H01L21/336;H01L27/12;H01L29/417;H01L29/786 |
主分类号 |
H01L29/78 |
代理机构 |
Robinson Intellectual Property Law Office, P.C. |
代理人 |
Robinson Eric J.;Robinson Intellectual Property Law Office, P.C. |
主权项 |
1. A semiconductor device comprising:
a first conductive layer; a first insulating layer whose side surface is in contact with a side surface of the first conductive layer; an oxide semiconductor layer over and in contact with the first conductive layer and the first insulating layer; a gate insulating layer over the oxide semiconductor layer; a gate electrode layer over the oxide semiconductor layer with the gate insulating layer interposed therebetween; a second insulating layer over the gate electrode layer; a first wiring layer over the second insulating layer, the first wiring layer being in contact with the first conductive layer through a first opening of the second insulating layer; a second wiring layer over the second insulating layer, the second wiring layer being in contact with the oxide semiconductor layer through a second opening of the second insulating layer; and a third wiring layer over the second insulating layer, the third wiring layer electrically connected to the oxide semiconductor layer through a third opening of the second insulating layer, wherein one surface of the oxide semiconductor layer is directly in contact with the first conductive layer. |
地址 |
Atsugi-shi, Kanagawa-ken JP |