Semiconductor device having a surround gate transistor

摘要

A semiconductor device includes a first-conductive type first pillar, a first dielectric surrounding the first pillar, a gate surrounding the dielectric, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface with the first pillar, and a first-conductive type region surrounded by the second-conductive type region. The third pillar has a second-conductive type impurity region in a surface thereof except a part of a contact surface with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region of the third pillar. The first-conductive type region of each of the second and third pillars has a length greater than that of a depletion layer extending from a base of the second-conductive type region of one of the second and third pillars.

主权项

1. A semiconductor device comprising:
a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar, wherein: the second silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region; and the third silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar, and wherein: the first-conductive type impurity region of the second silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the second silicon pillar; and the first-conductive type impurity region of the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the third silicon pillar.