Graphene devices with local dual gates

摘要

An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

主权项

1. A method of forming an electronic device comprising:
forming an insulator; embedding a local first gate and a local third gate in the insulator; planarizing a top surface of the local first gate, a top surface of the local third gate and a surface of the insulator such that the top surface of the local first gate, the top surface of the local third gate and the surface of the insulator are substantially coplanar; depositing a first dielectric layer over the local first gate, the local third gate and the insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer; and forming a local second gate and a local fourth gate over the second dielectric layer, each of the local first, second, third and fourth gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer and the local third and fourth gates form at least a second pair of gates to locally control a second portion of the bilayer graphene layer; wherein the first pair of gates operate as gates of a first transistor and the second pair of gates operate as gates of a second transistor; and wherein the first pair of gates and the second pair of gates provide independent control of a threshold voltage of the first transistor and a threshold voltage of the second transistor, respectively.