发明名称 CLOCK SUPPLY SYSTEM, CLOCK BUFFER GROUP, AND CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To achieve a clock supply system capable of synchronizing clock signals output from respective clock buffers, with a simple configuration.SOLUTION: A clock supply system comprises: a clock driver; and a plurality of clock buffers including one master and a plurality of slaves. The master comprises: first reception means for receiving a clock signal; calculation means for measuring clock response time with regard to the respective slaves to calculate delay amounts between the slaves; first transmission means for transmitting, on the basis of the delay amounts, an output instruction to adjust and output the clock signal, to each of the slaves; and first output means for delaying and outputting the clock signal on the basis of the response time. The slave comprises: second reception means for receiving the clock signal; and second output means for adjusting and outputting the clock signal on the basis of the output instruction.
申请公布号 JP2015126314(A) 申请公布日期 2015.07.06
申请号 JP20130268404 申请日期 2013.12.26
申请人 NEC PLATFORMS LTD 发明人 KOIKE KATSUYA
分类号 H04L7/00 主分类号 H04L7/00
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