发明名称 Digital duty cycle correction circuit
摘要 A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.
申请公布号 US9071237(B2) 申请公布日期 2015.06.30
申请号 US201414207751 申请日期 2014.03.13
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Lee Cheon-Oh;Kim Tae-Pyeong;Choi Jung-Myung;Kim Sung-Jun;Song Ho-Bin;Lim Han-Kyul
分类号 H03K7/08;H03K5/156 主分类号 H03K7/08
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A digital duty cycle correction circuit comprising: a duty cycle controller configured to generate a first output clock signal and a second output clock signal by compensating a duty cycle of a first input clock signal and a duty cycle of a second input clock signal based on a digital duty control code, the first and second input clock signals being a pair of differential signals, the first and second output clock signals being a pair of differential signals; and a digital duty control code generator configured to generate the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal, wherein the digital duty control code generator comprises: a monitor configured to generate a first direct current (DC) voltage and a second DC voltage by monitoring the first output clock signal and the second output clock signal;a voltage-frequency converter configured to generate a reference frequency signal, a first frequency signal and a second frequency signal by performing a voltage-frequency conversion on a reference voltage, the first DC voltage and the second DC voltage;a frequency counter configured to generate a reference count value, a first count value and a second count value by counting pulses of the reference frequency signal, pulses of the first frequency signal and pulses of the second frequency signal; anda digital state machine configured to generate the digital duty control code based on the reference count value, the first count value and the second count value.
地址 Suwon-si KR