发明名称 Semiconductor device and method of manufacturing the same
摘要 A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.
申请公布号 US9070690(B2) 申请公布日期 2015.06.30
申请号 US201313909551 申请日期 2013.06.04
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Suzumura Naohito;Oka Yoshihiro
分类号 H01L23/538;H01L21/768;H01L23/522;H01L23/532;H01L23/00 主分类号 H01L23/538
代理机构 Young & Thompson 代理人 Young & Thompson
主权项 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a second interlayer insulating film over a substrate; (b) forming a second wiring trench in an upper surface of the second interlayer insulating film to form a second wiring by embedding the second wiring in the second wiring trench; (c) supplying source gas including porogen to form a first interlayer insulating film over the second interlayer insulating film so as to cover the second wiring; (d) eliminating porogen from the first interlayer insulating film by performing UV curing; (e) after the (d) step, forming a via hole which passes through the first interlayer insulating film; (f) after the (d) step, forming a first wiring trench in an upper surface of the first interlayer insulating film; and (g) forming a via in the via hole and forming a first wiring by embedding the first wiring in the first wiring trench, wherein, the (c) step forms the first interlayer insulating film having a first film and a second film which includes more porogen than the first film, by increasing a porogen flow rate during the formation step of the first interlayer insulating film, wherein the (d) step forms a plurality of first vacancies in the first film and forms a plurality of second vacancies having an average diameter larger than an average diameter of the first vacancies in the second film, by eliminating the porogen, and wherein the (f) step forms a third film, including a plurality of third vacancies having an average diameter smaller than the average diameter of the second vacancies, on a side wall of the first wiring trench by forming the first wiring trench by plasma etching.
地址 Kanagawa JP