| 主权项 |
1. A Liquid Crystal Display (LCD) device comprising:
a data driver controlling a consumption power of an output buffer which outputs an image data signal to a data line formed in a liquid crystal display panel; a detection unit detecting a low power driving mode interval for driving the data driver at a first consumption power during a vertical blank interval, in which no image is output, of a vertical sync signal, the vertical blank interval being generated at every time between frames; and a power mode control option generation unit transferring a second power mode control option to the data driver during an interval other than the low power driving mode interval, and transferring a first power mode control option to the data driver during the low power driving mode interval, wherein the second power mode control option allows the data driver to be driven at a second consumption power, the first power mode control option allows the data driver to be driven at the first consumption power, and the first consumption power has a value less than the second consumption power, wherein the data driver changes a resistance value according to the first power mode control option or the second power mode control option, and controls a current value applied to the output buffer by changing the resistance value to control the consumption power of the output buffer, whereby the data driver is driven at the first consumption power during the vertical blank interval and is driven at the second consumption power during the interval other than the vertical blank interval, and wherein the data driver further comprises:
the output buffer outputting the image data signal to the liquid crystal display panel; anda power control circuit switching on to select one resistance value from among at least two or more different resistance values according to the first power mode control option or second power mode control option, and outputting a current, having a value which is set according to the selected resistance value, to the output buffer,wherein the power control circuit comprises a plurality of switches equal to a number of bits of the first power mode control option or second power mode control option, wherein the resistance value is selected according to the number of switches that are selected from among the plurality of switches according to the first power mode control option or second power mode control option. |
