CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE

摘要

An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

主权项

1. An apparatus for storing and providing configuration data to a multi-core processor, the apparatus comprising:
a plurality of cores, disposed on a die; and a fuse array, disposed on said die and coupled to each of said plurality of cores, wherein said fuse array comprises:
a first plurality of semiconductor fuses that is programmed with compressed configuration data for said each of said plurality of cores; anda second plurality of semiconductor fuses that is programmed with core designation data that associates some of said compressed configuration data with one of said plurality of cores, wherein said one of said plurality of cores accesses and decompresses said some of said compressed configuration data upon power-up/reset, for initialization of elements within said one of said plurality of cores.