发明名称 RESISTANCE-CHANGE NONVOLATILE MEMORY DEVICE
摘要 A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.
申请公布号 US2015179251(A1) 申请公布日期 2015.06.25
申请号 US201514635297 申请日期 2015.03.02
申请人 Panasonic Intellectual Property Management Co., Ltd. 发明人 YOSHIMOTO YUHEI;SHIMAKAWA KAZUHIKO;KAWAI KEN;AZUMA RYOTARO
分类号 G11C13/00;H01L27/24;G11C29/00;H01L45/00 主分类号 G11C13/00
代理机构 代理人
主权项 1. A resistance-change nonvolatile memory device comprising: a memory cell array having a plurality of memory cells arrayed in a matrix, each of the plurality of memory cells including a resistance change element and a selection element connected in series to the resistance change element, the resistance change element including a first electrode, a second electrode, and a resistance change layer between the first electrode and the second electrode, a resistance value of the resistance change layer changing reversibly based on electrical signals of different polarities applied between the first electrode and the second electrode, the resistance change layer including a first resistance change layer in contact with the first electrode and a second resistance change layer in contact with the second electrode, the first resistance change layer including a first metal oxide having a first degree of oxygen deficiency, the second resistance change layer including a second metal oxide having a second degree of oxygen deficiency, the second degree of oxygen deficiency being lower than the first degree of oxygen deficiency of the first metal oxide; a selection circuit that selects a memory cell from the memory cell array; and a read circuit that reads a resistance state of the resistance change element included in the selected memory cell, wherein the memory cell array comprises a multilayer memory cell array, in the multilayer cell array an odd-numbered wiring layer including a plurality of first wires being stacked on an even-numbered wiring layer including a plurality of second wires intersecting with the plurality of first wires, and in the multilayer cell array the plurality of the memory cells being provided at sections where the plurality of first wires included in the odd-numbered wiring layer intersect with the plurality of second wires included in the even-numbered wiring layer, the odd-numbered wiring layer and the even-numbered wiring layer being adjacent to each other in the stacking direction, wherein the multilayer memory cell array includes an odd-numbered-layer memory cell array on the odd-numbered wiring layer and an even-numbered-layer memory cell array on the even-numbered wiring layer, each memory cell in both of the odd-numbered-layer memory cell array and the even-numbered-layer memory cell array has the selection element, the first electrode, the first resistance change layer, the second resistance change layer, and the second electrode that are disposed in the same order, wherein the read circuit includes a first sense amplifier and a second sense amplifier, the first sense amplifier reading the resistance state of each memory cell included in the odd-numbered-layer memory cell array, the second sense amplifier reading the resistance state of each memory cell included in the even-numbered-layer memory cell array, and wherein irrespective of whether the selected memory cell is located in the odd-numbered-layer memory cell array or in the even-numbered-layer memory cell array, each of the first sense amplifier and the second sense amplifier applies to the selected memory cell a first voltage that causes the second electrode of the selected memory cell to become positive with reference to the first electrode of the selected memory cell.
地址 Osaka JP