发明名称 MEMORY DEVICE
摘要 According to one embodiment, a memory device includes a plurality of first interconnects extending in a first direction, and having divided portions formed respectively in the first interconnects at mutually-different positions in the first direction, a plurality of semiconductor members, each of the semiconductor members being disposed to extend over the first interconnects, a first insulating film disposed to cause each of the semiconductor members to be respectively connected to each of the first interconnects between portions of the first interconnects on two sides of the divided portions and to cause each of the semiconductor members to be insulated from other one of the first interconnects, a second insulating film provided on the semiconductor members, an electrode provided on the second insulating film, a memory cell member provided on the first interconnects, and a second interconnect provided on the memory cell member.
申请公布号 US2015171320(A1) 申请公布日期 2015.06.18
申请号 US201414206567 申请日期 2014.03.12
申请人 Kabushiki Kaisha Toshiba 发明人 Nishihara Kiyohito;Saitoh Masumi
分类号 H01L45/00 主分类号 H01L45/00
代理机构 代理人
主权项 1. A memory device, comprising: a plurality of first interconnects extending in a first direction, divided portions being formed respectively in the plurality of first interconnects at mutually-different positions in the first direction; a plurality of semiconductor members, each of the plurality of semiconductor members being disposed to extend over the plurality of first interconnects; a first insulating film disposed to cause each of the semiconductor members to be respectively connected to each of the first interconnects between portions of the first interconnects on two sides of the divided portions and to cause each of the semiconductor members to be insulated from other one of the first interconnects; a second insulating film provided on the semiconductor members; an electrode provided on the second insulating film; a memory cell member provided on the first interconnects; and a second interconnect provided on the memory cell member.
地址 Minato-ku JP