发明名称 異方性導電フィルム、異方性導電フィルムの製造方法、電子部品の接続方法、異方性導電接続体
摘要 <p><P>PROBLEM TO BE SOLVED: To prevent the warpage or the crack of a chip component by including an elastic spacer in an anisotropic conductive layer. <P>SOLUTION: A conductive grain containing layer 2 and an insulating resin layer 3 are laminated to make a multilayer structure so as to have the elastic spacer 4 in the boundary between the conductive grain containing layer 2 and the insulating resin layer 3. The hardness (20% K value) of the elastic spacer 4 is 20-500 kgf/mm<SP>2</SP>and the particle diameter D of the same is 10-50μm. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP5738013(B2) 申请公布日期 2015.06.17
申请号 JP20110049133 申请日期 2011.03.07
申请人 发明人
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
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