发明名称 |
Apparatus and method for performing a convert-to-integer operation |
摘要 |
A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value. |
申请公布号 |
US9059726(B2) |
申请公布日期 |
2015.06.16 |
申请号 |
US201213469109 |
申请日期 |
2012.05.11 |
申请人 |
ARM Limited |
发明人 |
Lutz David Raymond;Burgess Neil |
分类号 |
H03M7/24;G06F9/30;H03M7/28 |
主分类号 |
H03M7/24 |
代理机构 |
Nixon & Vanderhye P.C. |
代理人 |
Nixon & Vanderhye P.C. |
主权项 |
1. A data processing apparatus comprising:
processing circuitry configured to perform a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value, said floating-point value having a significand and an exponent; wherein said convert-to-integer operation uses round-to-nearest, ties away from zero, rounding in which a fractional floating-point value lying between two adjacent integer values is rounded to the nearest adjacent integer value, with a fractional floating-point value lying halfway between two adjacent integer values being rounded to the one of the two adjacent integer values lying furthest away from zero; said processing circuitry comprises intermediate value generating circuitry configured to generate an intermediate value based on said floating-point value, and adding circuitry configured to add a rounding value to the intermediate value to generate a sum value; said processing circuitry is configured to output the integer-valued bits of the sum value as the rounded two's complement integer value; and if said floating-point value has a negative value, then said intermediate value generating circuitry is configured to generate said intermediate value by inverting the bits of the significand of said floating-point value without adding a bit value of 1 to a least significant bit of the inverted value, wherein the rounding value has the same value irrespective of whether the floating-point value has a positive value or a negative value. |
地址 |
Cambridge GB |