发明名称 Crest factor reduction
摘要 A system for crest factor reduction (CFR) includes a peak detector configured to receive an input signal (xk); a running maximum filter configured to generate a scaling factor based on a window gain (Gk) and a filter length, wherein the window gain (Gk) is based on the input signal (xk) and a threshold value (T); a window CFR gain filter configured to generate a gain correction (Fk) based on the scaling factor and the filter length; a delay configured to delay the input signal (xk) to generate a delayed input signal; a multiplier configured to multiply the gain correction (Fk) by the delayed input signal to obtain a peak correction value; and an adder configured to determine an output signal (yk) based on the peak correction value and the delayed input signal.
申请公布号 US9054928(B1) 申请公布日期 2015.06.09
申请号 US201414444612 申请日期 2014.07.28
申请人 XILINX, INC. 发明人 Copeland Gregory C.
分类号 H04L27/26;H04B1/04 主分类号 H04L27/26
代理机构 代理人 Chan Gerald
主权项 1. A system for crest factor reduction (CFR), comprising: a peak detector configured to receive an input signal (xk); a running maximum filter configured to generate a scaling factor based on a window gain (Gk) and a filter length, wherein the window gain (Gk) is based on the input signal (xk) and a threshold value (T); a window CFR gain filter configured to generate a gain correction (Fk) based on the scaling factor and the filter length; a delay configured to delay the input signal (xk) to generate a delayed input signal; a multiplier configured to multiply the gain correction (Fk) by the delayed input signal to obtain a peak correction value; and an adder configured to determine an output signal (yk) based on the peak correction value and the delayed input signal; wherein the peak detector, the running maximum filter, the window CFR gain filter, the delay, the multiplier, the adder, or any combination of the foregoing, is implemented in at least one integrated circuit.
地址 San Jose CA US