主权项 |
1. A packet processing apparatus, comprising:
a packet processing engine (PPE) configured to process a packet and determine the packet is a processed fast path packet or a processed slow path packet; a receiving queue configured to store the processed fast path packet; a first packet direct memory access (PDMA) controller configured to forward the processed fast path packet, which is stored in the receiving queue, to an output queue which is a subsystem of a central processing unit (CPU) system; a second packet direct memory access controller configured to receive the processed fast path packet from the output queue; and a forwarding queue connected to the second PDMA controller for storing the processed fast path packet,
wherein the fast path packet is a packet which is processed by the PPE without by a CPU core included in the CPU system, and the slow path packet is a packet which is processed by both the PPE and the CPU core. |