发明名称 DATA PROCESSING IN A MULTIPLE PROCESSOR SYSTEM
摘要 A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover is positioned closer to the main memory and is connected to the cache memories of the at least one shared cache level (L2, L3, L4), the main memory and to the multiple processors to move data between the cache memories of the at least one shared cache level, the main memory and the processors. In response to a request from one of the processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories and the main memory maintaining multiple processor cache memory access coherency.
申请公布号 US2015154116(A1) 申请公布日期 2015.06.04
申请号 US201414543319 申请日期 2014.11.17
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Dittrich Jens;Jacobi Christian;Pflanz Matthias;Schuh Stefan;Weber Kai
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A data processing system comprising: at least one page mover positioned closer to a main memory and is connected to cache memories of at least one cache level shared between multiple processors, said main memory and to multiple processors to move data between said cache memories of said at least one cache level, said main memory and said multiple processors, wherein in response to a request from one requesting processor of said multiple processors, said at least one page mover fetches data of a storage area line-wise from at least one of the following memories: said cache memories of said at least one cache level or said main memory maintaining multiple processor cache memory access coherency; wherein said at least one page mover comprises a data processing engine which performs at least one of the following data processing operations: aggregation or filtering of the fetched data; and wherein said page mover moves processed data to at least one of the following components: cache memories of said at least one cache level, said main memory or the requesting processor maintaining multiple processor cache memory access coherency.
地址 Armonk NY US