| 摘要 |
Disclosed is a clock recovery method for a data receiving unit (1, fig.1). The data receiver may comprise sampling latches (2, fig.1), a multiphase generator (3, fig.1), and a clock recovery unit (5, fig.1) controlling a phase rotation unit (4, fig 1). The method, which may be carried out in the clock recovery unit (5, fig.1), comprises the steps of: obtaining an early/late signal E/L from an incoming data stream DI, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream DI is earlier or later than an edge of a clock signal phase-rotated by an amount depending on a phase offset value PR; updating a phase rotation counter value phtot in response to the early/late signal; and providing the phase offset value PR depending on a rounded phase rotation counter value phtot; wherein the phase offset value PR is determined by a look-ahead function 19, 20 which maintains, increments or decrements the rounded phase rotation counter value phtot depending on the early/late signal E/L and on the phase rotation counter value phtot. The system reduces latency and jitter. |
