DUT CONTINUITY TEST WITH ONLY DIGITAL IO STRUCTURES APPARATUS AND METHODS ASSOCIATED THEREOF

摘要

A method and system for determining short, open, and good connections using digital input and output (IO) structures in a device under test (DUT) continuity test, through the combined methods of using resistance-capacitance (RC) delay, time domain reflectometry (TDR), and forcing voltage on to a single IO pin of the DUT while measuring voltage on remaining IO pins of said DUT. In one embodiment, the combined methods are executed without the DUT in a test socket to produce a first set of test values and also with the DUT in a test socket to produce a second set of test values. The first and second sets of test values are compared to determine if one or more circuits of the DUT have a short circuit, an open circuit, or are a good (have an electrical connection that is not a short circuit or an open circuit) circuit.

主权项

1. A non-transitory machine readable medium configured to store a plurality of non-transitory machine readable instructions adapted to operate a computer and control equipment connected to said computer comprising:
a first plurality of non-transitory machine readable processing sequences comprising instructions to operate an electrical signal measuring section to measure resistor-capacitor (RC) delay on a circuit associated with a device under test (DUT) input/output (I/O) element; a second plurality of non-transitory machine readable processing sequences comprising instructions to operate said electrical signal measuring section to determine if said circuit associated with said DUT is an open circuit based on time domain reflectometry (TDR) associated with at least said DUT I/O element; and a third plurality of non-transitory machine readable processing sequence comprising instructions to operate said electrical signal measuring section to determine if said circuit associated with said DUT has a short circuit by applying voltage on said I/O element while measuring voltage on other I/O elements of said circuit of said DUT.