System and method for improving error distribution in multi-level memory cells

摘要

A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.

主权项

1. A system comprising:
a state set module configured to
arrange a plurality of states of a memory cell in (i) a first state set, (ii) a second state set, and (iii) a third state set,wherein the memory cell is configured to store (i) a first bit, (ii) a second bit, and (iii) a third bit in response to being programmed to one of the plurality of states,wherein each of the first state set, the second state set, and the third state set includes (i) a first row of bits including the first bits of the plurality of states, (ii) a second row of bits including the second bits of the plurality of states, and (iii) a third row of bits including the third bits of the plurality of states,wherein the first row of bits of the first state set (i) is identical to the second row of bits of the second state set and the third row of bits of the third state set and (ii) includes a first number of state transitions,wherein the second row of bits of the first state set (i) is identical to the third row of bits of the second state set and the first row of bits of the third state set and (ii) includes a second number of state transitions,wherein the third row of bits of the first state set (i) is identical to the first row of bits of the second state set and the second row of bits of the third state set and (ii) includes a third number of state transitions; and a write module configured to
receive data for writing to a plurality of memory cells, wherein each memory cell of plurality of memory cells is configured to store (i) the first bit, (ii) the second bit, and (iii) the third bit in response to being programmed to one of the plurality of states,write a first portion of the data to the plurality of memory cells using states from the first state set,write a second portion of the data to the plurality of memory cells using states from the second state set, andwrite a third portion of the data to the plurality of memory cells using states from the third state set.