Versatile lane configuration using a PCIe PIe-8 interface

摘要

Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

主权项

1. A computing device, comprising:
a first interface comprising hardware modules configured to support at least a first lane configuration and a second lane configuration for transmitting data in a PCI type connection; a second interface comprising hardware modules configured to support at least the first lane configuration and the second lane configuration; a bus comprising a plurality of lanes for transmitting data between the first and second interfaces; and at least two bus controllers configured to selectively provide access between the hardware modules of the first and second interfaces and the bus, wherein the hardware modules of the first and second interfaces use at least one of the plurality of lanes when transmitting data in the first lane configuration that is also used when transmitting data in the second lane configuration, wherein the first and second lane configurations are allocated at least one lane of the bus to create at least one PCI type link, and wherein the hardware modules of the first and second interfaces are coupled to the at least two bus controllers by interconnects that are not shared by any other hardware modules in the first and second interfaces.