COVERAGE ENHANCEMENT AND POWER AWARE CLOCK SYSTEM FOR STRUCTURAL DELAY-FAULT TEST

摘要

Methods and devices applying to a clock system of scan circuits to enhance the test coverage for structural delay-fault tests are provided. According to an aspect, a method applying to a clock system of a scan circuit of a scan test containing one or more clock gating cells includes at any stage of the scan test outputting a controllable waveform of a clock signal at each clock gating cell, and eliminating a partially enabled clock signal during a capture cycle at each clock gating cell.

主权项

1. A method applying to a clock system of a scan circuit of a scan test containing one or more clock gating cells, comprising
(a) at any stage of the scan test outputting a controllable waveform of a clock signal at each clock gating cell; and (b) eliminating a partially enabled clock signal during a capture cycle at each clock gating cell.