发明名称 STRESS INDUCING CONTACT METAL IN FINFET CMOS
摘要 A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer.
申请公布号 US2015137181(A1) 申请公布日期 2015.05.21
申请号 US201314083544 申请日期 2013.11.19
申请人 International Business Machines Corporation 发明人 Basker Veeraraghavan S.;Cheng Kangguo;Khakifirooz Ali;Koburger, III Charles W.
分类号 H01L27/092;H01L29/78;H01L21/8238 主分类号 H01L27/092
代理机构 代理人
主权项 1. A method of forming a semiconductor structure, the method comprising: forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate; forming a gate structure covering a first portion of the first plurality of fins and a first portion of the second plurality of fins, the gate structure not covering a second portion of the first plurality of fins and a second portion of the second plurality of fins; growing a first epitaxial layer surrounding the second portion of the first plurality of fins after forming the gate structure; growing a second epitaxial layer surrounding the second portion of the second plurality of fins after forming the gate structure, wherein the epitaxial layer surrounding one fin in the second region contacts the epitaxial layer of an adjacent fin in the second region; depositing an interlayer dielectric (ILD) layer above the semiconductor substrate; etching the ILD layer to remove the ILD layer in the second portion of the first region and the ILD layer in the second portion of the second region; and depositing a metal layer around the first epitaxial layer and above the top portion of the second epitaxial layer.
地址 Armonk NY US