发明名称 |
METHOD AND APPARATUS FOR DELIVERING MSI-X INTERRUPTS THROUGH NON-TRANSPARENT BRIDGES TO COMPUTING RESOURCES IN PCI-EXPRESS CLUSTERS |
摘要 |
An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources. |
申请公布号 |
US2015143016(A1) |
申请公布日期 |
2015.05.21 |
申请号 |
US201314083206 |
申请日期 |
2013.11.18 |
申请人 |
Futurewei Technologies, Inc. |
发明人 |
EGI Norbert;LASATER Robert;BOYLE Thomas;PETERS John;SHI Guangyu |
分类号 |
G06F13/32;G06F13/42 |
主分类号 |
G06F13/32 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus, comprising:
a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI Express (PCIe) fabric, wherein said management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein said target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to said PCIe fabric; a mapping module of said management I/O device controller configured for mapping said target interrupt register address to a mapped interrupt register address of a domain in which said first I/O device resides; and a translating interrupt register table comprising a plurality of mapped interrupt register addresses in said domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources. |
地址 |
Plano TX US |