Semiconductor device and fabricating the same

摘要

The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire.

主权项

1. A method for fabricating an integrated circuit device, the method comprising:
providing a precursor, the precursor including: a substrate having a first metal-oxide-semiconductor (MOS) region and a second MOS region; first gate and source/drain regions formed in the first MOS region, the first gate region including a first semiconductor layer stack; and second gate and source/drain regions formed in the second MOS region, the second gate region including a second semiconductor layer stack; laterally exposing the first semiconductor layer stack in the first gate region; oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, the first inner nanowire extending from the first source region to the first drain region; removing the first outer oxide layer to expose the first inner nanowire in the first gate region; forming a first high-k/metal gate (HK/MG) stack wrapping around the first inner nanowire; laterally exposing the second semiconductor layer stack in the second gate region; oxidizing the second semiconductor layer stack to form a second outer oxide layer and a second inner nanowire, the second inner nanowire extending from the second source region to the second drain region; removing the second outer oxide layer to expose the second inner nanowire in the second gate region; and forming a second HK/MG stack wrapping around the second inner nanowire.