发明名称 データプロセッサ
摘要 <p>The invention provides a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.</p>
申请公布号 JP5717896(B2) 申请公布日期 2015.05.13
申请号 JP20140050049 申请日期 2014.03.13
申请人 发明人
分类号 G06F9/48;G06F15/78 主分类号 G06F9/48
代理机构 代理人
主权项
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