WAFER LEVEL PACKAGING TECHNIQUES

摘要

In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

主权项

1. A packaged integrated circuit (IC) structure comprising:
a first substrate comprising a CMOS device and a CMOS bond ring, a second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring, and a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering an outer sidewall of the first substrate and does not cover an outer sidewall of the second substrate.