主权项 |
1. A glitch free multi-clock control circuit comprising
a plurality of clock gater circuits, each having a clock input, a gate input, and a gated clock output; an OR gate having inputs and an output, each said input being connected to a corresponding gated clock output of said clock gater circuits; and a latch corresponding to each said clock gater circuit, each said latch having a clock input, a set input, and an output, wherein said output is connected to said gate input of said corresponding clock gater circuit;wherein each of said plurality of clock gater circuits further comprises
a clock gater latch having an inverting clock input, a gate input, and an output; a delay cell having an input and an output; and an AND gate having a first and a second input and an output; wherein
said gate input of said clock gater latch is connected to said gate input of said clock gater circuit;said inverting clock input is connected to said input of said delay cell and to said clock input of said clock gater circuit;said output of said delay cell is connected to said second input of said AND gate;said output of said clock gater latch is connected to said first input of said AND gate; andsaid output of said AND gate is connected to said gated clock output of said clock gater circuit. |