Drive circuit of liquid crystal panel

摘要

The present invention provides a drive circuit of liquid crystal panel, which includes a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines. The plurality of gate lines and data lines define a plurality of pixel units. Each of the pixel units includes a thin-film transistor, a common electrode, a pixel electrode electrically connected to the thin-film transistor, and a correction capacitor. The thin-film transistor is electrically connected to the gate driver and the source driver respectively by means of the gate lines and the data lines. The common electrode and the pixel electrode constitute a liquid crystal capacitor. The thin-film transistor includes a gate terminal and a drain terminal. The correction capacitor is electrically connected between the gate terminal and the drain terminal for correcting a parasitic capacitor generated between the gate terminal ad the drain terminal due to structural characteristics.

主权项

1. A drive circuit of liquid crystal panel, comprising a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units, each of the pixel units comprising a thin-film transistor, a common electrode, a pixel electrode electrically connected to the thin-film transistor, and a correction capacitor, the thin-film transistor being electrically connected to the gate driver and the source driver respectively by means of the gate lines and the data lines, the common electrode and the pixel electrode constituting a liquid crystal capacitor, the thin-film transistor comprising a gate terminal and a drain terminal, the correction capacitor being electrically connected between the gate terminal and the drain terminal for correcting a parasitic capacitor generated between the gate terminal and the drain terminal due to structural characteristics;
wherein the correction capacitor is a voltage regulation capacitor having a capacitance that is smaller than a capacitance of the parasitic capacitor that is generated between the gate terminal and the drain terminal due to structural characteristics thereof and connected in parallel with the correction capacitor, and thereby the correction capacitor gets saturated earlier than the parasitic capacitor during charging effected by a rising edge of a gate voltage supplied to the gate terminal and the parasitic capacitor is constrained to be non-saturated; wherein the correction capacitor has a rating voltage that is smaller than a rating voltage of the parasitic capacitor that is generated between the gate terminal and the drain terminal due to structural characteristics thereof.