| 发明名称 |
NEARLY BUFFER ZONE FREE LAYOUT METHODOLOGY |
| 摘要 |
In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities. |
| 申请公布号 |
US2015108610(A1) |
申请公布日期 |
2015.04.23 |
| 申请号 |
US201414578690 |
申请日期 |
2014.12.22 |
| 申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Peng Yung-Chow;Horng Jaw-Juinn;Liu Szu-Lin;Kang Po-Zeng |
| 分类号 |
H01L27/02 |
主分类号 |
H01L27/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit, comprising:
a central array region having a first layout feature density; a background region surrounding the central array region and having a second layout feature density, which is different from the first density; and a peripheral array region surrounding the central array region and separating the central array region from the background region, wherein the peripheral array region has a third layout feature density between the first and second layout feature densities. |
| 地址 |
Hsin-Chu TW |
