发明名称 KNAPSACK-BASED SHARING-AWARE SCHEDULER FOR COPROCESSOR-BASED COMPUTE CLUSTERS
摘要 A method is provided for controlling a compute cluster having a plurality of nodes. Each of the plurality of nodes has a respective computing device with a main server and one or more coprocessor-based hardware accelerators. The method includes receiving a plurality of jobs for scheduling. The method further includes scheduling the plurality of jobs across the plurality of nodes responsive to a knapsack-based sharing-aware schedule generated by a knapsack-based sharing-aware scheduler. The knapsack-based sharing-aware schedule is generated to co-locate together on a same computing device certain ones of the plurality of jobs that are mutually compatible based on a set of requirements whose fulfillment is determined using a knapsack-based sharing-aware technique that uses memory as a knapsack capacity and minimizes makespan while adhering to coprocessor memory and thread resource constraints.
申请公布号 US2015113542(A1) 申请公布日期 2015.04.23
申请号 US201414506256 申请日期 2014.10.03
申请人 NEC Laboratories America, Inc. 发明人 Cadambi Srihari;Coviello Giuseppe;Chakradhar Srimat
分类号 G06F9/52;H04L29/08 主分类号 G06F9/52
代理机构 代理人
主权项 1. A method for controlling a compute cluster having a plurality of nodes, each of the plurality of nodes having a respective computing device with a main server and one or more coprocessor-based hardware accelerators, the method comprising: receiving a plurality of jobs for scheduling; and scheduling the plurality of jobs across the plurality of nodes responsive to a knapsack-based sharing-aware schedule generated by a knapsack-based sharing-aware scheduler, wherein the knapsack-based sharing-aware schedule is generated to co-locate together on a same computing device certain ones of the plurality of jobs that are mutually compatible based on a set of requirements whose fulfillment is determined using a knapsack-based sharing-aware technique that uses memory as a knapsack capacity and minimizes makespan while adhering to coprocessor memory and thread resource constraints.
地址 Princeton NJ US