Chipset support for non-uniform memory access among heterogeneous processing units

摘要

A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.

主权项

1. A method for providing a first processor access to a physical memory associated with a second processor included in a computer system, the method comprising:
receiving a first address map from the first processor that includes a memory-mapped input/output (I/O) aperture for a non-uniform memory access (NUMA) device that the first processor is configured to access, wherein the NUMA device comprises an enumerated hardware device coupled to an input/output (I/O) controller, and wherein the memory-mapped I/O aperture provides the first processor memory-mapped I/O access to the NUMA device; receiving a second address map from the second processor that includes memory-mapped I/O apertures for a set of hardware devices that the second processor is configured to access; generating a global address map by combining the first address map and the second address map; receiving a first access request transmitted from the first processor to the NUMA device, whereby the first processor requests access to the physical memory associated with the second processor; generating a memory access request based on the first access request and based on a translation table for translating memory mapped I/O addresses into physical addresses associated with a physical memory, wherein the translation table maps a first address associated with the first access request into a second address associated with the physical memory associated with the second processor; and routing the memory access request to the physical memory based on the global address map to cause a memory bridge associated with the second processor to:
determine that the first access request is a cache-coherent access request;determine that a cache associated with the second processor is coherent with the physical memory associated with the second processor; andin response to determining that the cache is coherent, access data in the physical memory associated with the second processor based on the memory access request.