Recessed transistor and method of manufacturing the same

摘要

A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

主权项

1. A recessed transistor, comprising:
an isolation layer that establishes an active region and a field region of a substrate; a recessed structure having an upper recess on a surface portion of the active region and a lower recess in communication with the upper recess; an active pin in the active region and interposed between side surfaces of the isolation layer and the lower recess and between interfaces of the active region and the field region, wherein the active pin encloses the lower recess of the recessed structure in a cross sectional direction along a width of the recessed transistor; a gate insulation layer on a side surface and a bottom surface of the recessed structure; a gate electrode on the gate insulation layer in the recessed structure and on the isolation layer, the gate electrode having a linear shape extending on the gate insulation layer and the isolation layer in the cross sectional direction along the width of the recessed transistor; and source and drain regions in the active region adjacent to the gate electrode, wherein the active pin includes a first active pin portion and a second active pin portion in the cross sectional direction, the first and second active pin portions having top surfaces lower than a top surface of the isolation layer, the first active pin portion, the lower recess and the second active pin portion are interposed between side surfaces of the isolation layer in the cross sectional direction along the width of the recessed transistor, and a width of the lower recess in the cross sectional direction is less than a width of the upper recess in the cross sectional direction.