发明名称 Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM
摘要 A computer or microchip including a system BIOS located in flash memory which is located in a portion of the computer or microchip protected by an inner hardware-based access barrier or firewall, a central controller of the computer or microchip having a connection by a secure control bus with other parts of the computer or microchip, and a volatile random access memory located in a portion of the computer or microchip that has a connection for a network. The secure control bus is isolated from input from the network, and provides and ensures direct preemptive control by the central controller over the volatile random access memory, the control including transmission to or erasure of data and/or code in the volatile random access memory and control of a connection between the central controller, the volatile random access memory and at least one microprocessor having a connection for the network.
申请公布号 US9009809(B2) 申请公布日期 2015.04.14
申请号 US201414333759 申请日期 2014.07.17
申请人 发明人 Ellis Frampton E.
分类号 G06F15/173;G06F13/40;H04L29/06;G06F11/20;G06F21/71;G06F21/50;G06F21/85;G06F17/00 主分类号 G06F15/173
代理机构 Mendelsohn, Drucker & Dunleavy, P.C 代理人 Mendelsohn, Drucker & Dunleavy, P.C
主权项 1. A computer or microchip, comprising: a system BIOS of the computer or microchip located in flash memory which is located in a portion of the computer or microchip protected by an inner hardware-based access barrier or firewall; and a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with other parts of the computer or microchip, and including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has at least one connection for a network; the secure control bus is isolated from input from the network; the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM); the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and the direct preemptive control also includes control of a connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one or many microprocessors having a connection for the network.
地址