发明名称 GPU DIVERGENCE BARRIER
摘要 A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.
申请公布号 WO2015050681(A1) 申请公布日期 2015.04.09
申请号 WO2014US54966 申请日期 2014.09.10
申请人 QUALCOMM INCORPORATED 发明人 MEI, CHUNHUI;BOURD, ALEXEI VLADIMIROVICH;CHEN, LIN
分类号 G06F9/52 主分类号 G06F9/52
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