METHOD OF FABRICATING WAFER-LEVEL CHIP PACKAGE

摘要

A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

主权项

1. A method of fabricating a wafer-level chip package, comprising:
providing a wafer with at least two adjacent chips, the wafer having an upper surface and a lower surface, and at least one side of each chip includes a conducting pad on the lower surface; forming a recess extending from the upper surface to the lower surface to expose the conducting pad; forming an isolation layer extending from the upper surface to the lower surface, a part of the isolation layer disposed in the recess, wherein the isolation layer has an opening to expose the conducting pad; forming a conductive layer on the isolation layer and the conductive pad; spray coating a photo-resist layer on the conductive layer; exposing and developing the photo-resist layer to expose a part of the conductive layer; etching the part of the conductive layer to form a redistribution layer; stripping the photo-resist layer; and forming a solder layer on the isolation layer and the redistribution layer.