发明名称 |
Address generation unit using end point patterns to scan multi-dimensional data structures |
摘要 |
A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit. |
申请公布号 |
US9003165(B2) |
申请公布日期 |
2015.04.07 |
申请号 |
US200812331337 |
申请日期 |
2008.12.09 |
申请人 |
|
发明人 |
Rakib Shlomo Selim;Schaub Marc |
分类号 |
G06F17/30;G06F9/345;G06F9/38 |
主分类号 |
G06F17/30 |
代理机构 |
|
代理人 |
Zweig Stephen E. |
主权项 |
1. A method for operating a data system component comprising:
a data memory providing a multi-dimensional data structure; providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern; configuring the address generation unit to calculate the real addresses by moving across the multi-dimensional data structure between pairs of end points, wherein the pairs of end points are pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure, and using a vector processor unit to access the data structure at the real addresses calculated by the address generation unit; wherein said address generation unit comprises a buffer descriptor memory and a port descriptor memory; and using said address generation unit to generate real addresses in response to read/write requests from either a vector processor unit controller or a connection manager communicating with a bus whose primary responsibility is to transfer data; wherein said vector processor unit controller makes read or write requests to a connection as opposed to specifying the real address in said data memory where the read or write is to occur; and wherein said connection is identified by a connection identification composed of a buffer identification and a port identification. |
地址 |
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