On-chip probe circuit for detecting faults in an FPGA

摘要

An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.

主权项

1. An integrated circuit including:
a clock input; a first output; a second output; a fixed delay element having an input coupled to the clock input and an output; a programmable delay element having an input coupled to the clock input, an output, and at least one control input for receiving delay information; a first multiplexer having a first data input coupled to the output of the fixed delay element, a second data input coupled to the output of the programmable delay element, an output coupled to the first output, and a control input; and a second multiplexer having a first data input coupled to the output of the programmable delay element, a second data input coupled to the output of the fixed delay element, an output coupled to the second output, and a control input.