| 发明名称 |
NONVOLATILE MEMORY STRUCTURE |
| 摘要 |
A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel. |
| 申请公布号 |
US2015091074(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201414477818 |
申请日期 |
2014.09.04 |
| 申请人 |
eMemory Technology Inc. |
发明人 |
Hsu Te-Hsun;Chen Wei-Ren;Chen Hsuen-Wei;Tsao Mu-Ying;Chen Ying-Je |
| 分类号 |
H01L27/115;H01L29/49;H01L29/423 |
主分类号 |
H01L27/115 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A nonvolatile memory cell unit, comprising:
a P type substrate; an N well in the P type substrate; and a PMOS storage transistor disposed on the N well, wherein the PMOS storage transistor comprises a floating gate, a P+ drain doping region, a common P+ doping region, a floating gate dielectric layer between the floating gate and the N well, a floating gate channel between the P+ drain doping region and the common P+ doping region, and an auxiliary gate disposed in close proximity to one side of the floating gate, wherein a gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel. |
| 地址 |
Hsin-Chu TW |
