| 发明名称 |
Instruction and Logic for Machine Checking Communication |
| 摘要 |
A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank. |
| 申请公布号 |
US2015095705(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201314040092 |
申请日期 |
2013.09.27 |
| 申请人 |
RAJ ASHOK;KUMAR MOHAN J.;VARGAS JOSE A.;AULD WILLIAM G.;MCNAIRY CAMERON B.;YIGZAW THEODROS;CROSSLAND JAMES B.;LUCK ANTHONY E. |
发明人 |
RAJ ASHOK;KUMAR MOHAN J.;VARGAS JOSE A.;AULD WILLIAM G.;MCNAIRY CAMERON B.;YIGZAW THEODROS;CROSSLAND JAMES B.;LUCK ANTHONY E. |
| 分类号 |
G06F11/07 |
主分类号 |
G06F11/07 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor, comprising:
a first logic to determine an error condition reported in an error bank, the error bank communicatively coupled to the processor and associated with a plurality of logical processors of the processor; a second logic to generate an interrupt indicating the error condition; and a third logic to selectively send the interrupt to a single one of the plurality of logical processors associated with the error bank. |
| 地址 |
PORTLAND OR US |
