Display device and driving method thereof

摘要

To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light. Through the operation process, a current obtained by compensating variations in the threshold voltage of the first transistor can be supplied to the light-emitting element, thereby variations in luminance can be suppressed.

主权项

1. A display device comprising:
a light-emitting element; a first transistor connected to the light-emitting element; a second transistor; a third transistor; a fourth transistor; a first storage capacitor; a second storage capacitor; a first line capable of supplying a first potential to be input to one of source and drain of the first transistor, wherein the first potential is a power supply potential; a second line capable of supplying a video signal; and a third line capable of supplying a second potential that is different from the first potential, wherein a gate terminal of the first transistor is connected to a first electrode of the first storage capacitor, wherein the one of source and drain of the first transistor is connected to the first line, wherein one of source and drain of the second transistor is directly connected to the other one of source and drain of the first transistor and is directly connected to a first electrode of the light-emitting element, wherein the other one of source and drain of the second transistor is directly connected to the gate terminal of the first transistor, wherein one of source and drain of the third transistor is connected to the second line, wherein the other one of source and drain of the third transistor is connected to a second electrode of the first storage capacitor, wherein one of source and drain of the fourth transistor is connected to the third line, wherein the other one of source and drain of the fourth transistor is connected to the second electrode of the first storage capacitor, wherein a first electrode of the second storage capacitor is connected to the other one of source and drain of the second transistor, and wherein a second electrode of the second storage capacitor is connected to the third line.