发明名称 Semiconductor integrated circuit
摘要 An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
申请公布号 US8988124(B2) 申请公布日期 2015.03.24
申请号 US201113292133 申请日期 2011.11.09
申请人 Renesas Electronics Corporation 发明人 Yokoyama Masanao;Okuzono Noboru
分类号 H03K3/289;H03K3/356;H03K3/012;H03K3/3562 主分类号 H03K3/289
代理机构 Young & Thompson 代理人 Young & Thompson
主权项 1. A semiconductor integrated circuit comprising: a D-FF circuit; and a switch control circuit, wherein the D-FF circuit includes an input buffer that chooses, in accordance with a first control clock, to output an input data signal or output a high-impedance signal,a master flip-flop that chooses, in accordance with a second control clock to output a data signal received from the input buffer or retain a currently output data signal,a master-slave switch that chooses, in accordance with a second control clock, to output a high-impedance signal or output a data signal received from the master flip-flop, anda slave flip-flop that chooses, in accordance with a second control clock, to retain a currently output data signal or output a data signal received from the master-slave switch, wherein the input buffer does not receive the second control clock, wherein none of the master flip-flop, the master-slave switch, and the slave flip-flop receive the first control clock, and wherein the switch control circuit includes: a first clock buffer that receives an external clock and outputs the second control clock, anda second clock buffer that receives the second control clock, retards rising and/or falling edges of the second control clock, and outputs the first control clock.
地址 Kanagawa JP