Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory

摘要

Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.

主权项

1. A method for sensing in a 3d non-volatile memory device, comprising:
selecting a set of memory cells in a selected word line layer of a plurality of word line layers to sense data, the plurality of word line layers are arranged alternatingly with dielectric layers in a stack, and memory cells in the set of memory cells in the selected word line layer are arranged in respective memory holes which extend through the stack, the respective memory holes having respective widths which vary along the memory holes; and in response to the selecting, sensing the set of memory cells in the selected word line layer, the sensing comprises applying a sense voltage to the selected word line layer while applying read pass voltages to unselected word line layers of the plurality of word line layers, wherein the read pass voltages are relatively lower for word line layers of the unselected word line layers which are adjacent to relatively narrower portions of the memory holes.