METHOD OF FABRICATING INTEGRATED CIRCUITS, PROVIDING IMPROVED SO-CALLED SAW BOWS

摘要

An integrated circuit (6) has a semiconductor die (47) and an integrated circuit configuration (16) realized on the semiconductor die (47) and situated within bounding faces (52, 53, 54, 55) of the semiconductor die (47), in which two conductor track sections (34, 35) have been provided, which issue from the integrated circuit configuration (16) and which each extend up to a bounding face (55) and which are required for the application of a useful signal (BR1) utilized for test purposes during the fabrication of the integrated circuit (6), and in which an additional conductor track section (41) has been provided, which is disposed adjacent the two conductor track sections (34, 35) and which issues from the integrated circuit configuration (16) and extends toward a bounding surface (55) and preferably up to this bounding face (55) and which serves for the application of a spurious signal (BR2) which interferes with testing.