Multi chip package

摘要

The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate.

主权项

1. A multi chip package, comprising:
a printed circuit board on which a cavity is formed; a first semiconductor chip, a face surface of the first semiconductor chip being disposed on one surface of the printed circuit board including the cavity in a face-down manner; and a second semiconductor chip disposed on the first semiconductor chip in a face-up manner; wherein a first metal wire for electrical connection from a first electrode terminal formed on the face surface of the first semiconductor chip is connected to a circuit pattern including a first via on the other surface of the printed circuit hoard, a second metal wire more extendedly formed than the first metal wire for electrical connection from a second electrode terminal formed on one surface of the second semiconductor chip is connected to a circuit pattern Including a second via on one surface of the printed circuit board, and electrical conductivity of a material filled in the second via is larger than that of a material filled in the first via.