| 摘要 |
A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned. |
| 主权项 |
1. A Spatial Wavefunction Switching CMOS (SWS-CMOS) like logic inverter, comprising:
a first field-effect transistor device having a first source region, a first gate region, and a first drain region, and a second field-effect transistor device having a second source region, a second gate region, and a second drain region, wherein the first field-effect transistor and the second field-effect transistor are n-channel devices each having n-channel structures and are configured to form the inverter,
wherein each of the n-channel structures include an upper quantum well W1 and at least one lower quantum well W2,wherein the upper quantum well W1 is sandwiched between a gate insulator and a first barrier layer, wherein the thickness of the gate insulator of the first field-effect transistor differs from the thickness of the gate insulator of the second field-effect transistor and are sized responsive to a threshold used to form an inversion channel, andwherein the lower quantum well W2 is sandwiched between the first barrier layer of the upper quantum well and a second barrier layer on its bottom side, wherein the second barrier layer is interfaced with a p-semiconductor region, andwherein each of the two upper and lower quantum wells are electrically connected with the source and drain regions, wherein the source and drain regions are n-type and electrically form a connection with the carriers introduced in the quantum wells to form the inversion channels, andwherein the first field-effect transistor has the lower quantum well W2 on a source side and is connected to a drain end of the upper quantum well W1 of the second field-effect transistor, and the drain end of the first field-effect transistor is connected to a voltage supply, wherein a source end of the second field-effect transistor is connected to at least one of a ground or a second voltage supply, the gates of the first and second field-effect transistors being electrically connected to each other, andwherein the gates of the first and second field-effect transistors are also connected to an input voltage, andwherein a source end of the lower quantum well W2 of the first transistor which is connected to the drain end of the upper quantum well W1 of the second transistor T2 is also connected to the output, the output end is connected to other logic stages. |
