Semiconductor memory device capable of performing refresh operation without auto refresh command

摘要

A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

主权项

1. A semiconductor memory device, comprising:
an internal address generating circuit configured to analyze an external address and to control timing of the external address to generate an internal address; an internal command generating circuit configured to control timing of an auto refresh operation based on the external address and an external command and to control timing of the external command to generate an internal command; and a memory cell array including one or more memory bank groups, each of the one or more memory bank groups including a plurality of memory banks and operating in response to the internal address and the internal command, wherein, when a read command or a write command is input, if a first portion of the plurality of memory banks of a first memory bank group from among the one or more memory bank groups performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation, the first portion including one or more of the plurality of memory banks of the first memory bank group, the second portion including the one or more of the plurality of memory banks of the first memory bank group which are not included in the first portion.